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19-1453; Rev 0; 6/99
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
General Description
The MAX3140 is a complete universal asynchronous receiver-transmitter (UART) and a true fail-safe RS485/RS-422 transceiver combined in a single 28-pin QSOP package for space-, cost-, and power-constrained applications. The MAX3140 saves additional board space as well as microcontroller (C) I/O pins by featuring an SPITM/QSPITM/MICROWIRETM-compatible serial interface. It is pin-programmable for configuration in all RS-485/RS-422 networks. The MAX3140 includes a single RS-485/RS-422 driver and receiver featuring true fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted. This feature provides immunity to faults without requiring complex termination. The MAX3140 provides software-selectable control of half- or full-duplex operation, data rate, slew rate, and transmitter and receiver phase. The RS-485 driver slew rate is programmable to minimize EMI and results in maximum data rates of 115kbps, 500kbps, and 10Mbps. Independent transmitter/receiver phase control enables software correction of twisted-pair polarity reversal. A 1/8-unit-load receiver input impedance allows up to 256 transceivers on the bus. The MAX3140's UART includes an oscillator circuit derived from an external crystal, and a baud-rate generator with software-programmable divider ratios for all common baud rates from 300 baud to 230k baud. The UART features an 8-word-deep receive FIFO that minimizes processor overhead and provides a flexible interrupt with four maskable sources, including address recognition on 9-bit networks. Two control lines are included for hardware handshaking--one input and one output. The MAX3140 operates from a single +5V supply and typically consumes only 645A with the receiver active. Hardware-invoked shutdown reduces supply current to only 20A. The UART and RS-485/RS-422 functions can be used together or independently since the two functions share only supply and ground connections (the MAX3140 is hardware- and software-compatible with the MAX3100 and MAX3089).
Features
o Integrated UART and RS-485/RS-422 Transceiver in a Single 28-Pin QSOP o SPI/MICROWIRE-Compatible Interface Saves C I/O Pins o True Fail-Safe Receiver Output Eliminates Complex Network Termination o Pin-Programmable RS-485/RS-422 Features Half/Full-Duplex Operation Slew-Rate Limiting for Reduced EMI 115kbps/500kbps/10Mbps Data Rates Receiver/Transmitter Phase for Twisted-Pair Polarity Reversal o Full-Featured UART Programmable Up to 230k baud with a 3.6864MHz Crystal 8-Word Receive FIFO Minimizes Processor Overhead 9-Bit Address-Recognition Interrupt o Allows Up to 256 Transceivers on the Bus o Low 20A Hardware Shutdown Mode o Hardware/Software-Compatible with MAX3100 and MAX3089
MAX3140
Ordering Information
PART MAX3140CEI MAX3140EEI TEMP. RANGE 0C to +70C -40C to +85C PIN-PACKAGE 28 QSOP 28 QSOP
Typical Application Circuit
MAX3140
SPI/ MICROWIRE CS SCLK DIN DOUT IRQ Rt CONTROL LOGIC RS-485 RS-422 Rt UART
Applications
Industrial-Control Local Area Networks HVAC and Building Control Point-of-Sale Devices Transceivers for EMISensitive Applications Embedded Systems Intelligent Instrumentation
P
SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Pin Configuration appears at end of data sheet.
H/F SRL TXP RXP
HALF/FULL-DUPLEX RS-485/RS-422
________________________________________________________________ Maxim Integrated Products
1
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..........................................................................+6V Input Voltage to GND (CS, SHDN, X1, CTS, RX, DIN, SCLK, RE, DE, H/F, SRL, TXP, RXP, Dl) .............-0.3V to (VCC + 0.3V) Output Voltage to GND DOUT, RTS, TX, X2, RO...........................-0.3V to (VCC + 0.3V) IRQ ........................................................................-0.3V to +6V Driver Output Voltage (Y, Z) ...............................................13V Receiver Input Voltage, Half Duplex (Y, Z)......................... 13V Receiver Input Voltage, Full Duplex (A, B) .........................25V TX, RTS Output Current ...................................................100mA X2, DOUT, IRQ Short-Circuit Duration (to VCC or GND) ......................................................Continuous Continuous Power Dissipation (TA = +70C) 28-pin QSOP (derate 10.8mW/C above +70C)..........860mW Operating Temperature Ranges MAX3140CEI .......................................................0C to +70C MAX3140EEI ....................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5V 5%, DE = VCC, RE = GND, SHDN = VCC, fXTL = 1.8432MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured with VCC = +5V, UART configured for 9600 baud, TA = +25C.) (Note 1) PARAMETER POWER SUPPLY Supply Voltage VCC SHDN = VCC; SHDNi bit = 0, no load SRL = VCC SRL = GND or open DE = VCC DE = GND DE = VCC DE = GND 4.75 0.7 0.64 0.74 0.69 0.47 5.25 1.9 1.6 2 1.8 1 mA mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current
ICC
Supply Current with Only UART ICC SHDN Shut Down UART Supply Current with Both RS-485 Transceiver and UART Shut Down Input High Voltage Input Low Voltage Input Current Input Capacitance Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance UART OUTPUTS (DOUT, TX, RTS) Output High Voltage Output Low Voltage Output Leakage Output Capacitance 2 VOH1 VOL1 ILKG2 COUT1 ICC SHDN (FULL)
SHDN = GND or SHDNi bit = 1 SHDN = GND or SHDNi bit = 1; DE = GND; RE = VCC
20
A
UART OSCILLATOR INPUT (X1) VIH1 VIL1 IIN1 CIN1 VIH2 VIL2 VHYST2 ILKG1 CIN2 ISOURCE = 5mA; DOUT, RTS ISOURCE = 10mA; TX only ISINK = 4mA; DOUT, RTS ISINK = 25mA; TX only CS = VCC; DOUT only 5 VCC - 0.5 VCC - 0.5 0.4 0.9 1 5 250 1 0.7VCC 0.3VCC VX1 = 0 or VCC SHDNi bit = 0 SHDNi bit = 1 5 0.7VCC 0.2VCC 25 2 V V A pF V V mV A pF
UART LOGIC INPUTS (DIN, SCLK, CS, SHDN, CTS, RX)
V V A pF
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V 5%, DE = VCC, RE = GND, SHDN = VCC, fXTL = 1.8432MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured with VCC = +5V, UART configured for 9600 baud, TA = +25C.) (Note 1) PARAMETER Output Low Voltage Output Leakage Output Capacitance RS-485 DRIVER VOD1 Differential Output Voltage Change in Magnitude of Differential Output Voltage Common-Mode Output Voltage Change In Magnitude of Common-Mode Voltage Input High Voltage Input Low Voltage DI Input Hysteresis Input Current SRL Input High Voltage SRL Input Middle Voltage SRL Input Low Voltage SRL Input Current Full-Duplex Input Current (A and B) Full-Duplex Output Leakage (Y and Z) Short-Circuit Output Current RS-485 RECEIVER Differential Threshold Voltage Input Hysteresis Output High Voltage Output Low Voltage Three-State Output Current Input Resistance Output Short-Circuit Current VTH VTH VOH VOL IOZR RIN IOSR ISOURCE = 4mA, VID = -50mV ISINK = 4mA, VID = -200mV 0.4V VO 2.4V -7V VCM 12V 0 VRO VCC 96 7 95 VCC - 1.5 0.4 1 -7V VCM +12V -200 -125 25 -50 mV mV V V A k mA 3 VOD2 VOD VOC VOC VIH1 VIL1 VHYS IIN1 IIN2 VIH2 VIM2 VIL2 IIN3 IIN4 IO SRL = VCC SRL = GND (Note 3) DE = GND VCC = GND or 5.25V DE = GND VCC = GND or 5.25V (Note 4) VIN = 12V VIN = -7V VIN = 12V VIN = -7V -7V VOUT VCC IOSD 0 VOUT 12V 0 VOUT VCC 25 -100 -250 250 mA -75 125 -75 125 (Note 3) No load, Figure 1 R = 50 (RS-422), Figure 1 R = 27 (RS-422), Figure 1 R = 50 or R = 27, Figure 1 (Note 2) R = 50 or R = 27, Figure 1 R = 50 or R = 27, Figure 1 (Note 2) DE, Dl, RE H/F, TXP, RXP DE, Dl, RE, H/F, TXP, RXP SRL = VCC or unconnected DE, DI, RE H/F, TXP, RXP, internal pull-down 10 VCC - 0.8 0.4 * VCC 0.6 * VCC 0.8 75 100 2 40 2.0 2.4 0.8 2.0 1.5 0.2 3 0.2 V V V V V mV A V V V A A A 5 V SYMBOL VOL2 ILKG3 COUT2 ISINK = 4mA V IRQ = VCC 5 CONDITIONS MIN TYP MAX 0.4 1 UNITS V A pF UART IRQ OUTPUT (Open Drain)
MAX3140
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
UART SWITCHING CHARACTERISTICS
(VCC = +5V 5%, fXTL = 1.8432MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured with VCC = +5V, UART configured for 9600 baud, TA = +25C.) (Note 1) PARAMETER UART AC TIMING (Figure 1) CS Low to DOUT Valid CS High to DOUT Tri-State CS to SCLK Setup Time CS to SCLK Hold Time SCLK Fall to DOUT Valid DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Period SCLK High Time SCLK Low Time SCLK Rising Edge to CS FaIling CS Rising Edge to SCLK Rising CS High Pulse Width Output Rise Time Output Fall Time tDV tTR tCSS tCSH tDO tDS tDH tCP tCH tCL tCS0 tCS1 tCSW tr tf TX, RTS, DOUT; CLOAD = 100pF TX, RTS, DOUT, IRQ; CLOAD = 100pF CLOAD = 100pF 100 0 238 100 100 100 200 200 10 10 CLOAD = 100pF CLOAD = 100pF, R CS = 10k 100 0 100 100 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
4
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
SWITCHING CHARACTERISTICS--SRL = Unconnected
(VCC = +5V 5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25C.) PARAMETER Driver Input to Output Driver Output Skew | tDPLH - tDPHL | Driver Rise or Fall Time Maximum Data Rate Driver Enable to Output High Driver Enable to Output Low Driver Disable Time from Low Driver Disable Time from High Receiver Input to Output SYMBOL tDPLH tDPHL tDSKEW tDR, tDF fMAX tDZH tDZL tDLZ tDHZ tRPLH, tRPHL tRSKD tRZL tRZH tRLZ tRHZ tSHDN tDZH(SHDN) tDZL(SHDN) tRZH(SHDN) tRZL(SHDN) Figures 4 and 6, CL = 100pF, S2 closed Figures 4 and 6, CL = 100pF, S1 closed Figures 4 and 6, CL = 15pF, S1 closed Figures 4 and 6, CL = 15pF, S2 closed Figures 7 and 9, | VID | 2.0V, rise and fall time of VID 15ns Figures 7 and 9, | VID | 2.0V, rise and fall time of VID 15ns Figures 2 and 8, CL = 100pF, S1 closed Figures 2 and 8, CL = 100pF, S2 closed Figures 2 and 8, CL = 100pF, S1 closed Figures 2 and 8, CL = 100pF, S2 closed (Note 5) Figures 4 and 6, CL = 15pF, S2 closed Figures 4 and 6, CL = 15pF, S1 closed Figures 2 and 8, CL = 100pF, S2 closed Figures 2 and 8, CL = 100pF, S1 closed 50 127 3 20 20 20 20 200 CONDITIONS Figures 3 and 5, RDIFF = 54, CL1 = CL2 = 100pF Figures 3 and 5, RDIFF = 54, CL1 = CL2 = 100pF Figures 3 and 5, RDIFF = 54, CL1 = CL2 = 100pF 667 115 3500 3500 100 100 200 30 50 50 50 50 600 6000 6000 3500 3500 MIN 500 500 TYP 2030 2030 -3 1320 MAX 2600 2600 200 2500 UNITS ns ns ns kbps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX3140
| tRPLH - tRPHL | Differential Receiver Skew
Receiver Enable to Output Low Receiver Enable to Output High Receiver Disable Time from Low Receiver Disable Time from High Time to Shutdown Driver Enable from Shutdown to Output High Driver Enable from Shutdown to Output Low Receiver Enable from Shutdown to Output High Receiver Enable from Shutdown to Output Low
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
SWITCHING CHARACTERISTICS--SRL = VCC
(VCC = +5V 5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25C.) PARAMETER Driver Input to Output Driver Output Skew | tDPLH - tDPHL | Driver Rise or Fall Time Maximum Data Rate Driver Enable to Output High Driver Enable to Output Low Driver Disable Time from Low Driver Disable Time from High Receiver Input to Output SYMBOL tDPLH tDPHL tDSKEW tDR, tDF fMAX tDZH tDZL tDLZ tDHZ tRPLH, tRPHL tRSKD tRZL tRZH tRLZ tRHZ tSHDN tDZH(SHDN) tDZL(SHDN) tRZH(SHDN) tRZL(SHDN) Figures 4 and 6, CL = 100pF, S2 closed Figures 4 and 6, CL = 100pF, S1 closed Figures 4 and 6, CL = 15pF, S1 closed Figures 4 and 6, CL = 15pF, S2 closed Figures 7 and 9, | VID | 2.0V, rise and fall time of VID 15ns Figures 7 and 9, | VID | 2.0V, rise and fall time of VID 15ns Figures 2 and 8, CL = 100pF, S1 closed Figures 2 and 8, CL = 100pF, S2 closed Figures 2 and 8, CL = 100pF, S1 closed Figures 2 and 8, CL = 100pF, S2 closed (Note 5) Figures 4 and 6, CL = 15pF, S2 closed Figures 4 and 6, CL = 15pF, S1 closed Figures 2 and 8, CL = 100pF, S2 closed Figures 2 and 8, CL = 100pF, S1 closed 50 127 3 20 20 20 20 200 CONDITIONS Figures 3 and 5, RDIFF = 54, CL1 = CL2 = 100pF Figures 3 and 5, RDIFF = 54, CL1 = CL2 = 100pF Figures 3 and 5, RDIFF = 54, CL1 = CL2 = 100pF 200 500 2500 2500 100 100 200 30 50 50 50 50 600 4500 4500 3500 3500 MIN 250 250 TYP 720 720 -3 530 MAX 1000 1000 100 750 UNITS ns ns ns kbps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
| tRPLH - tRPHL | Differential Receiver Skew Receiver Enable to Output Low
Receiver Enable to Output High Receiver Disable Time from Low Receiver Disable Time from High Time to Shutdown Driver Enable from Shutdown to Output High Driver Enable from Shutdown to Output Low Receiver Enable from Shutdown to Output High Receiver Enable from Shutdown to Output Low
6
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
SWITCHING CHARACTERISTICS--SRL = GND
(VCC = +5V 5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25C.) PARAMETER Driver Input to Output Driver Output Skew | tDPLH - tDPHL | Driver Rise or Fall Time Maximum Data Rate Driver Enable to Output High Driver Enable to Output Low Driver Disable Time from Low Driver Disable Time from High Receiver Input to Output SYMBOL tDPLH tDPHL tDSKEW tDR, tDF fMAX tDZH tDZL tDLZ tDHZ tRPLH, tRPHL tRSKD tRZL tRZH tRLZ tRHZ tSHDN tDZH(SHDN) tDZL(SHDN) tRZH(SHDN) tRZL(SHDN) Figures 4 and 6, CL = 100pF, S2 closed Figures 4 and 6, CL = 100pF, S1 closed Figures 4 and 6, CL = 15pF, S1 closed Figures 4 and 6, CL = 15pF, S2 closed Figures 7 and 9, | VID | 2.0V, rise and fall time of VID 15ns Figures 7 and 9, | VID | 2.0V, rise and fall time of VID 15ns Figures 2 and 8, CL = 100pF, S1 closed Figures 2 and 8, CL = 100pF, S2 closed Figures 2 and 8, CL = 100pF, S1 closed Figures 2 and 8, CL = 100pF, S2 closed (Note 5) Figures 4 and 6, CL = 15pF, S2 closed Figures 4 and 6, CL = 15pF, S1 closed Figures 2 and 8, CL = 100pF, S2 closed Figures 2 and 8, CL = 100pF, S1 closed 50 106 0 20 20 20 20 200 CONDITIONS Figures 3 and 5, RDIFF = 54, CL1 = CL2 = 100pF Figures 3 and 5, RDIFF = 54, CL1 = CL2 = 100pF Figures 3 and 5, RDIFF = 54, CL1 = CL2 = 100pF 10 150 150 100 100 150 10 50 50 50 50 600 250 250 3500 3500 MIN TYP 34 34 -2.5 14 MAX 60 60 10 25 UNITS ns ns ns Mbps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX3140
| tRPLH - tRPHL | Differential Receiver Skew Receiver Enable to Output Low
Receiver Enable to Output High Receiver Disable Time from Low Receiver Disable Time from High Time to Shutdown Driver Enable from Shutdown to Output High Driver Enable from Shutdown to Output Low Receiver Enable from Shutdown to Output High Receiver Enable from Shutdown to Output Low
Note 1: All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device ground unless otherwise noted. Note 2: VOD and VOC are the changes in VOD and VOC, respectively, when the Dl input changes state. Note 3: The SRL pin is internally biased to VCC/2 by a 100k/100k resistor-divider. It is guaranteed to be VCC/2 if left unconnected. Note 4: Maximum current level applies to peak current just prior to foldback-current limiting; minimum current level applies during current limiting. Note 5: The device is put into shutdown by bringing RE high and DE low. If the enable inputs are in this state for less than 50ns, the device is guaranteed not to enter shutdown. If the enable inputs are in this state for at least 600ns, the device is guaranteed to have entered shutdown.
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Typical Operating Characteristics
(VCC = +5V, TA = +25C, unless otherwise noted.)
UART SUPPLY CURRENT vs. TEMPERATURE
MAX3140-01
UART SHUTDOWN CURRENT vs. TEMPERATURE
MAX3140-02
UART SUPPLY CURRENT vs. BAUD RATE
1.8432 MHz CRYSTAL
MAX3140-03
1000 900 800 SUPPLY CURRENT (A) 700 600 500 400 300 200 100 0 -40 -20 0 20 40 60 80 1.8432MHz CRYSTAL TRANSMITTING AT 115.2 kbps
10 9 SHUTDOWN CURRENT (A) 8
1.8432MHz CRYSTAL
400 350 SUPPLY CURRENT (A) 300 STANDBY 250 200 150 100 50 TRANSMITTING
7 6 5 4 3 2 1 0
100
-40
-20
0
20
40
60
80
100
100
1000
10k BAUD RATE (bps)
100k
1M
TEMPERATURE (C)
TEMPERATURE (C)
UART SUPPLY CURRENT vs. EXTERNAL CLOCK FREQUENCY
MAX3140-04
TX, RTS, DOUT OUTPUT CURRENT vs. OUTPUT LOW VOLTAGE
MAX3140-05
RS-485 TRANSCEIVER NO-LOAD SUPPLY CURRENT vs. TEMPERATURE
A: SRL = GND DE = VCC A DE = GND B A B B: SRL = OPEN OR VCC -60 -40 -20 0 20 40 60 80 100 500 475 450 425 400 375 350 325 300
MAX3140-06
700 600 SUPPLY CURRENT (A) 500 400 300 200 100 0 0 1 2 3 4 5 EXTERNAL CLOCK FREQUENCY (MHz)
90 80 OUTPUT SINK CURRENT (mA) 70 60 50 40 30 20 10 0 DOUT RTS TX
525 NO-LOAD SUPPLY CURRENT (A)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT LOW VOLTAGE (V)
TEMPERATURE (C)
RS-485 OUTPUT CURRENT vs. RECEIVER OUTPUT LOW VOLTAGE
MAX3140-07
RS-485 OUTPUT CURRENT vs. RECEIVER OUTPUT HIGH VOLTAGE
MAX3140-08
RS-485 TRANSCEIVER SHUTDOWN CURRENT vs. TEMPERATURE
18 SHUTDOWN CURRENT (nA) 16 14 12 10 8 6 4 2
MAX3140-09
60 50 OUTPUT CURRENT (mA) 40 30 20 10 0 0 1 2 3 4 5 OUTPUT LOW VOLTAGE (V)
30 25 OUTPUT CURRENT (mA) 20 15 10 5 0 0 1 2 3 4 5 OUTPUT HIGH VOLTAGE (V)
20
0 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
8
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
Typical Operating Characteristics (continued)
(VCC = +5V, TA = +25C, unless otherwise noted.)
MAX3140
RS-485 RECEIVER OUTPUT LOW VOLTAGE vs. TEMPERATURE
MAX3140-10
RS-485 RECEIVER OUTPUT HIGH VOLTAGE vs. TEMPERATURE
MAX3140-11
RS-485 RECEIVER PROPAGATION DELAY (500kbps MODE) vs. TEMPERATURE
CLOAD = 100pF PROPAGATION DELAY (ns) 135 130
MAX3140-12
0.50 IRO = 8mA 0.45 OUTPUT LOW VOLTAGE (V) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -60 -40 -20 0 20 40 60 80
4.5 IRO = 8mA 4.4 OUTPUT HIGH VOLTAGE (V) 4.3 4.2 4.1 4.0 3.9 3.8
140
125
120
115 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C)
100
TEMPERATURE (C)
RS-485 RECEIVER PROPAGATION DELAY (10Mbps MODE) vs. TEMPERATURE
MAX3140-13
RS-485 DRIVER PROPAGATION DELAY (115kbps MODE) vs. TEMPERATURE
MAX3140-14
RS-485 DRIVER PROPAGATION DELAY (500kbps MODE) vs. TEMPERATURE
880 PROPAGATION DELAY (ns) 840 800 760 720 680 640 600 560 Rt = 54
MAX3140-15
112 110 PROPAGATION DELAY (ns) 108 106 104 102 100 98 96 94 -60 -40 -20 0 20 40 60 80 CLOAD = 100pF
2.20 Rt = 54 2.15 PROPAGATION DELAY (s) 2.10 2.05 2.00 1.95 1.90
920
520 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C)
100
TEMPERATURE (C)
RS-485 DRIVER PROPAGATION DELAY (10Mbps MODE) vs. TEMPERATURE
MAX3140-16
RS-485 DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURE
MAX3140-17
RS-485 DRIVER OUTPUT CURRENT vs. DIFFERENTIAL OUTPUT VOLTAGE
MAX3140-18
60 55 PROPAGATION DELAY (ns) 50 45 40 35 30 25 20 -60 -40 -20 0 20 40 60 80 Rt = 54
1.90 Rt = 54 1.89 OUTPUT VOLTAGE (V) 1.88 1.87 1.86 1.85 1.84 1.83
100
OUTPUT CURRENT (mA) -60 -40 -20 0 20 40 60 80 100
10
1
0.1
0.01 0 1 2 3 4 5 TEMPERATURE (C) DIFFERENTIAL OUTPUT VOLTAGE (V)
100
TEMPERATURE (C)
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Typical Operating Characteristics (continued)
(VCC = +5V, TA = +25C, unless otherwise noted.)
OUTPUT CURRENT vs. RS-485 DRIVER OUTPUT LOW VOLTAGE
MAX3140-19
OUTPUT CURRENT vs. RS-485 DRIVER OUTPUT HIGH VOLTAGE
-90 -80 OUTPUT CURRENT (mA) -70 -60 -50 -40 -30 -20 RO (5V/div)
MAX3140-20
RS-485 RECEIVER PROPAGATION DELAY (SRL = GND)
MAX3140-21
140 120 OUTPUT CURRENT (mA) 100 80 60 40 20 0 0 2 4 6 8 10
-100
VA - VB (2V/div)
-10 0 12 -8 -6 -4 -2 0 2 4 6 50ns/div OUTPUT LOW VOLTAGE (V) OUTPUT HIGH VOLTAGE (V)
RS-485 RECEIVER PROPAGATION DELAY (SRL = OPEN OR VCC)
MAX3140-22
RS-485 DRIVER PROPAGATION DELAY (SRL = OPEN)
MAX3140-23
DI (5V/div) VA - VB (2V/div)
RO (5V/div)
VY - VZ (2.5V/div)
50ns/div
2s/div
RS-485 DRIVER PROPAGATION DELAY (SRL = VCC)
MAX3140-24
RS-485 DRIVER PROPAGATION DELAY (SRL = GND)
MAX3140-25
DI (5V/div)
DI (5V/div)
VY - VZ (2.5V/div)
VY - VZ (2.5V/div)
500ns/div
50ns/div
10
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
Pin Description
PIN FULL DUPLEX 1 2 3 4 5 6 7 8 9 10 11 12 HALF DUPLEX 1 2 3 4 5 6 7 8 9 10 11 12 NAME FUNCTION
MAX3140
X2 X1 CTS RTS RX TX H/F GND RO RE DE DI
UART Crystal Connection. Leave X2 unconnected for external clock. See the Crystals, Oscillators, and Ceramic Resonators section. UART Crystal Connection. X1 also serves as an external clock input. See the Crystals, Oscillators, and Ceramic Resonators section. UART Clear-to-Send Active-Low Input. Read via the CTS bit. UART Request-to-Send Active-Low Output. Controlled by the RTS bit. Use to control the driver enable in RS-485 networks. UART Asynchronous Serial-Data (receiver) Input. The serial information received from the modem or RS-232/RS-485 receiver. A transition on RX while in shutdown generates an interrupt (Table 1). UART Asynchronous Serial-Data (transmitter) Output RS-485 Half/Full-Duplex Selector Pin. Connect H/F to VCC for half-duplex mode; connect H/F to GND or leave it unconnected for full-duplex mode. Ground RS-485 Receiver Output. When RE is low and if A - B -50mV, RO will be high; if A - B -200mV, RO will be low. RS-485 Receiver Output Enable. Drive RE low to enable RO; RO is high impedance when RE is high. Drive RE high and DE low to enter low-power shutdown mode. RS-485 Driver Output Enable. Drive DE high to enable driver outputs. These outputs are high impedance when DE is low. Drive RE high and DE low to enter low-power shutdown mode. RS-485 Driver Input. With DE high, a low on DI forces noninverting output low and inverting output high. Similarly, a high on DI forces noninverting output high and inverting output low. RS-485 Transceiver Slew-Rate-Limit Selector Pin. Connect SRL to GND for a 10Mbps communication rate, connect SRL to VCC for a 500kbps rate, or leave SRL unconnected for a 115kbps rate. No Connection. Not internally connected. RS-485 Transmitter Phase. Connect TXP to GND or leave it floating for normal transmitter phase/polarity. Connect TXP to VCC to invert the transmitter phase/polarity. RS-485 Noninverting Driver Output RS-485 Noninverting Receiver Input and RS-485 Noninverting Driver Output* No Connection. Not internally connected. RS-485 Inverting Driver Output RS-485 Inverting Receiver Input and RS-485 Inverting Driver Output* RS-485 Inverting Receiver Input RS-485 Receiver Input Resistors* RS-485 Noninverting Receiver Input RS-485 Receiver Input Resistors*
13 14 15 16 -- 17 18 -- 19 -- 20 --
13 14 15 -- 16 17 -- 18 -- 19 -- 20
SRL N.C. TXP Y Y N.C. Z Z B B A A
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11
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Pin Description (continued)
PIN FULL DUPLEX 21 22 23 24 25 26 27 28 HALF DUPLEX 21 22 23 24 25 26 27 28 NAME FUNCTION
RXP VCC DIN DOUT SCLK CS IRQ SHDN
RS-485 Receiver Phase. Connect RXP to GND or leave it unconnected for normal receiver phase/polarity. Connect RXP to VCC to invert the receiver phase/polarity. Positive Supply (4.75V to 5.25V) UART SPI/MICROWIRE Serial-Data Input. Schmitt-trigger input. UART SPI/MICROWIRE Serial-Data Output. High impedance when CS is high. UART SPI/MICROWIRE Serial-Clock Input. Schmitt-trigger input. UART Active-Low Chip-Select Input. DOUT goes high impedance when CS is high. IRQ, TX, and RTS are always active. Schmitt-trigger input. UART Active-Low Interrupt Output. Open-drain interrupt output to microprocessor. UART Hardware Shutdown Input. When shut down (SHDN = 0), the UART oscillator turns off immediately without waiting for the current transmission to end, reducing the supply current to just leakage currents.
*In half-duplex mode, the driver outputs serve as receiver inputs. The full-duplex receiver inputs ( A and B) still have a 1/8-unit load, but do not affect the receiver output.
Transceiver Function Tables
TRANSMITTING INPUTS TXP 0 0 1 1 X X RE X X X X 0 1 DE 1 1 1 1 0 0 DI 1 0 1 0 X X OUTPUTS Z 0 1 1 0 High-Z Y 1 0 0 1 High-Z H/F 0 0 0 0 1 1 1 1 0 1 0 1 X X RXP 0 0 1 1 0 0 1 1 0 0 1 1 X X RE 0 0 0 0 0 0 0 0 0 0 0 0 1 1 RECEIVING INPUTS DE X X X X X X X X X X X X 1 0 A-B -0.05V -0.2V -0.05V -0.2V X X X X Open/ Shorted X Open/ Shorted X X X Y-Z X X X X -0.05V -0.2V -0.05V -0.2V X Open/ Shorted X Open/ Shorted X X OUTPUTS RO 1 0 0 1 1 0 0 1 1 1 0 0 High-Z Shutdown (High-Z)
Shutdown (High-Z)
12
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Y R VOD R Z VOC S2 TEST POINT S1 1k 1k VCC
RECEIVER OUTPUT
CL 15pF
Figure 1. Driver DC Test Load
Figure 2. Receiver Enable/Disable Timing Test Load
VCC DE DI Y VID Z
CL1 RDIFF OUTPUT UNDER TEST CL2 CL S2 500 S1 VCC
Figure 3. Driver Timing Test Circuit
Figure 4. Driver Enable/Disable Timing Test Load
3V DI 0 1.5V tPLH tPHL 1.5V DE
3V 1.5V 0 tZL(SHDN), tZL tLZ VOL +0.5V 1.5V
Z VO Y 1/2 VO VDIFF = V (Y) - V (Z) 10% tR tSKEW = | tPLH - tPHL | 90% 90% tF 10% 1/2 VO
Y, Z VOL Y, Z 2.3V 0 tZH(SHDN), tZH tHZ 2.3V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH VOH -0.5V
VDIFF
VO 0 -VO
Figure 5. Driver Propagation Delays
Figure 6. Driver Enable and Disable Times
13
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
3V RE 0 RO VOH VOL A B 1.5V tPHL INPUT RO 0 tZH(SHDN), tZH tHZ 1.5V OUTPUT tPLH 1.5V VCC RO tZL(SHDN), tZL tLZ VOL + 0.5V 1.5V 1.5V
1V -1V
1.5V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH
VOH - 0.5V
Figure 7. Receiver Propagation Delays
Figure 8. Receiver Enable and Disable Times
B ATE VID A RR RECEIVER OUTPUT
Figure 9. Receiver Propagation Delay Test Circuit
_______________Detailed Description
The MAX3140 combines an SPI/QSPI/MICROWIREcompatible UART (MAX3100) and an RS-485/RS-422 transceiver (MAX3089) in one package. The UART supports data rates up to 230k baud for both standard UART bit streams as well as IrDA, and includes an 8-word receive FIFO. Also included is a parity-bit interrupt useful in 9-bit address recognition. The RS-485/RS-422 transceiver has a true fail-safe receiver and allows up to 256 transceivers on the bus. Other features include pin-selectable full/half-duplex operation and a phase control to correct for twisted-
pair reversal. The slew rate of the RS-485/RS-422 transceiver is selectable, limiting the maximum data rate to 115kbps, 500kbps, or 10Mbps. The RS-485/RS-422 drivers are output short-circuit current limited, and thermal shutdown circuitry protects the RS-485/RS-422 drivers against excessive power dissipation. The UART and RS-485/RS422 functions can be used together or independently since the two functions only share supply and ground connections. This part operates from a single +5V supply.
14
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
UART
The universal asynchronous receiver transmitter (UART) interfaces the SPI/MICROWIRE-compatible synchronous serial data from a microprocessor (P) to asynchronous, serial-data communication ports (RS485, IrDA). Figure 10 shows the MAX3140 functional diagram. Included in the UART function is an SPI/MICROWIRE interface, a baud-rate generator, and an interrupt generator.
SPI Interface The MAX3140 is compatible with SPI, QSPI (CPOL = 0, CPHA = 0), and MICROWIRE serial-interface standards (Figure 11). The MAX3140 has a unique full-duplex architecture that expects a 16-bit word for DIN and simultaneously produces a 16-bit word for DOUT regardless of which read/write register used. The DIN stream is monitored for its first two bits to tell the UART the type of data transfer being executed (see the WRITE CONFIGURATION register, READ CONFIGURATION register, WRITE DATA register, and READ DATA register sections). DIN (MOSI) is latched on
MAX3140
RX BUFFER 9
Pr RE
A
MAX3140
IRQ
INTERRUPT LOGIC 9
9 RX FIFO
9 Pr
RO RXP
B
9 RX SHIFT REGISTSER Pr BAUD-RATE GENERATOR TX SHIFT REGISTSER Pt
RX X2 X1 TX TXP DI Z GND Y
DOUT SPI INTERFACE 4
SCLK CS DIN
9 9 TX BUFFER Pt CTS RTS NOTE: SWITCH POSITIONS INDICATE H/F = GND
SRL DE H/F
I/O
Figure 10. Functional Diagram
DIN DOUT CS SCLK (CPOL = 0, CPHA = 0) SCLK (CPOL = 0, CPHA = 1) SCLK (CPOL = 1, CPHA = 0) SCLK (CPOL = 1, CPHA = 1) NOT COMPATIBLE WITH MAX3140 COMPATIBLE WITH MAX3140 MSB MSB 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
Figure 11. Compatible CPOL and CPHA Modes
______________________________________________________________________________________ 15
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
SCLK's rising edge. DOUT (MISO) is read into the P on SCLK's rising edge. The first bit (bit 15) of DOUT transitions on CS's falling edge, and bits 14-0 transition on SCLK's falling edge. Figure 12 shows the detailed serial timing specifications for the synchronous SPI port. Only 16-bit words are expected. If CS goes high in the middle of a transmission (any time before the 16th bit), the sequence is aborted (i.e., data does not get written to individual registers). Most operations, such as the
CS tCSS tCH *** tDS tDH DIN tDV DOUT *** *** tDO tTR
clearing of internal registers, are executed only on CS's rising edge. Every time CS goes low, a new 16-bit stream is expected. Figure 13 shows an example of using the WRITE CONFIGURATION register. Table 1 describes the bits located in the WRITE CONFIGURATION, READ CONFIGURATION, WRITE DATA, and READ DATA registers. This table also describes whether the bit is a read or write bit and what the power-on reset states (POR) of the bits are. Figure 14 shows an example of parity and word length control.
***
tCSO SCLK
tCL
tCSH
tCS1
Figure 12. Detailed Serial Timing Specifications for the Synchronous Port
DATA UPDATED
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIN DOUT
1 R
1 T
FEN 0
SHDN 0
TM 0
RM 0
PM 0
RAM 0
IR 0
ST 0
PE 0
L 0
B3 0
B2 0
B1 0
B0 0
Figure 13. SPI Interface (Write Configuration)
PE = 0, L = 0 IDLE START D0 D1 D2 D3 D4 D5 D6 D7 STOP STOP IDLE
PE = 0, L = 1 IDLE START D0 D1 D2 D3 D4 D5 D6 STOP STOP IDLE
PE = 1, L = 0 IDLE START D0 D1 D2 D3 D4 D5 D6 D7 Pt STOP STOP IDLE
PE = 1, L = 1 IDLE TIME START D0 D1 D2 D3 D4 D5 D6 Pt STOP STOP IDLE
SECOND STOP BIT IS OMITTED IF ST = 0.
Figure 14. Parity and Word Length Control
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
Table 1. Bit Descriptions
BIT NAME B0-B3 B0-B3 CTS D0t-D7t D0r-D7r FEN FEN IR IR L L Pt BIT TYPE write read read write read write read write read write read write POR STATE 0000 0000 No change XXXXXXXX 00000000 0 0 0 0 0 0 X DESCRIPTION Baud-Rate Divisor Select Bits. Sets the baud clock's value (Table 6). Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers. Clear-to-Send-Input. Records the state of the CTS pin (CTS bit = 0 implies CTS pin = logic high). Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored when L = 1. Eight data bits read from the receive FIFO or the receive-buffer register. When L = 1, D7r is always 0. FIFO Enable. Enables the receive FIFO when FEN = 0. When FEN = 1, FIFO is disabled. FIFO-Enable Readback. FEN's state is read. Enables the IrDA timing mode when IR = 1. Reads the value of the IR bit. Bit to set the word length of the transmitted or received data. L = 0 results in 8-bit words (9-bit words if PE = 1) (see Figure 5). L = 1 results in 7-bit words (8-bit words if PE = 1). Reads the value of the L bit. Transmit-Parity Bit. This bit is treated as an extra bit that is transmitted if PE = 1. In 9-bit networks, the MAX3140 does not calculate parity. If PE = 0, then this bit (Pt) is ignored in transmit mode (see the 9-Bit Networks section). Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive data (see the 9-Bit Networks section). Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt bit as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to be received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3140 does not calculate parity. Reads the value of the Parity-Enable bit. Mask for Pr bit. IRQ is asserted if PM = 1 and Pr = 1 (Table 7). Reads the value of the PM bit (Table 7). Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read or is being read from the receive register or FIFO. If performing a READ DATA or WRITE DATA operation, the R bit will clear on the falling edge of SCLK's 16th pulse if no new data is available. Mask for R bit. IRQ is asserted if RM = 1 and R = 1 (Table 7). Reads the value of the RM bit (Table 7). Mask for RA/FE bit. IRQ is asserted if RAM = 1 and RA/FE = 1 (Table 7). Reads the value of the RAM bit (Table 7). Request-to-Send Bit. Controls the state of the RTS output. This bit is reset on power-up (RTS bit = 0 sets the RTS pin = logic high).
MAX3140
Pr
read
X
PE
write
0
PE PM PM R RM RM RAM RAM RTS
read write read read write read write read write
0 0 0 0 0 0 0 0 0
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17
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Table 1. Bit Descriptions (continued)
BIT NAME BIT TYPE POR STATE DESCRIPTION Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation, this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a framing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is expected. FE is set when a framing error occurs, and cleared upon receipt of the next properly framed character independent of the FIFO being enabled. When the device wakes up, it is likely that a framing error will occur. This error is cleared with a WRITE CONFIGURATION. The FE bit is not cleared on a READ DATA operation. When an FE is encountered, the UART resets itself to the state where it is looking for a start bit. Software-Shutdown Bit. Enter software shutdown with a WRITE CONFIGURATION where SHDNi = 1. Software shutdown takes effect after CS goes high, and causes the oscillator to stop as soon as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r-D7r, D0t-D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated while in shutdown. Exit software shutdown with a WRITE CONFIGURATION where SHDNi = 0. The oscillator restarts typically within 50ms of CS going high. RTS and CTS are unaffected. Refer to the Pin Description for hardware shutdown (SHDN input). Shutdown Read-Back Bit. The READ CONFIGURATION register outputs SHDNo = 1 when the UART is in shutdown. Note that this bit is not sent until the current byte in the transmitter is sent (T = 1). This tells the processor when it may shut down the RS-485/RS-422 driver. This bit is also set immediately when the device is shut down through the SHDN pin. Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmitted when ST = 1. The receiver only requires one stop bit. Reads the value of the ST bit. Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to accept another data word. Transmit-Enable Bit. If TE = 1, then only the RTS pin is updated on CS's rising edge. The contents of RTS, Pt, and D0t-D7t transmit on CS's rising edge when TE = 0. Mask for T Bit. IRQ is asserted if TM = 1 and T = 1 (Table 7). Reads the value of the TM bit (Table 7).
RA/FE
read
0
SHDNi
write
0
SHDNo
read
0
ST ST T TE TM TM
write read read write write read
0 0 1 0 0 0
Notice to High-Level Programmers The MAX3140 follows the SPI convention of providing a bidirectional data path for writes and reads. Whenever the data is written, data is also read back. This speeds operation over the SPI bus, as required, when operating at high baud rates. In most high-level languages, like C, there are commands for writing and reading stream I/O devices like the console or serial port. In C specifically, there is a "PUTCHAR" command that transmits a character and a "GETCHAR" command that receives a character. Implementing direct write and read commands in C with no underlying driver code causes an intended PUTCHAR command to become a PUTGETCHAR command. These C commands assume that they'll receive some form of BIOS-level support.
The proper way to implement these commands is to use driver code--usually in the form of an assembly language interrupt service routine and a callable routine used by high-level routines. This driver handles the interrupts and manages the receive and transmit buffers for the MAX3140. When a PUTCHAR executes, this driver is called and it safely buffers any characters received when the current character is transmitted. Likewise, when a GETCHAR executes, it checks its own receive buffer before getting data from the MAX3140. See the C-language outline of a MAX3140 software driver in Listing 1.
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
WRITE CONFIGURATION Register (D15, D14 = 1, 1) Configure the UART by writing a 16-bit word to the WRITE CONFIGURATION register, which programs the baud rate, data-word length, parity enable, and enable of the 8-word receive FIFO. Set bits 15 and 14 of the DIN configuration word to 1 to enable the WRITE CONFIGURATION mode. Bits 13-0 of the DIN configuration word set the configuration of the UART. Table 2 shows the bit assignment for the WRITE CONFIGURATION register. The WRITE CONFIGURATION register allows selection between normal UART timing and IrDA timing, shutdown control, and contains four interrupt mask bits.
Setting the WRITE CONFIGURATION register clears the receive FIFO and the R, T, RA/FE, D0r-D7r, D0t-D7t, Pr, and Pt registers. Bits RTS and CTS remain unchanged. The new configuration is valid on CS's rising edge if the transmit buffer is empty (T = 1) and transmission is over. If the latest transmission has not been completed (T = 0), the registers are updated when the transmission is over. The WRITE CONFIGURATION register bits (FEN, SHDNi, IR, ST, PE, L, B3-B0) take effect after the current transmission is over. The mask bits (TM, RM, PM, RAM) take effect immediately after SCLK's 16th rising edge.
MAX3140
Table 2. WRITE CONFIGURATION Register Bit Assignment (D15, D14 = 1, 1)
BIT DIN DOUT Notes: bit 15, 14: DIN 1, 1 = Write Configuration bit 13: DIN FEN = 0, FIFO is enabled FEN= 1, FIFO is disabled bit 12: DIN SHDNi = 1, Enter software shutdown SHDNi = 0, Exit software shutdown bit 11: DIN TM = 1, Transmit-buffer-empty interrupt is enabled. TM = 0, Transmit-buffer-empty interrupt is disabled. bit 10: DIN RM = 1, Data available in the receive register or FIFO interrupt is enabled. RM = 0, Data available in the receive register or FIFO interrupt is disabled. bit 9: DIN PM = 1, Parity-bit-received interrupt is enabled. PM = 0, Parity-bit-received interrupt is disabled. bit 8: DIN RAM = 1, Receiver-activity (shutdown mode)/Framing-error (normal operation) interrupt is enabled. RAM = 0, Receiver-activity (shutdown mode)/Framing-error (normal operation) interrupt is disabled. 15 1 R 14 1 T 13 FEN 0 12 SHDNi 0 11 TM 0 10 RM 0 9 PM 0 8 RAM 0 7 IR 0 6 ST 0 5 PE 0 4 L 0 3 B3 0 2 B2 0 1 B1 0 0 B0 0
bit 7: DIN IR = 1, IrDA mode is enabled. IR = 0, IrDA mode is disabled. bit 6: DIN ST = 1, Transmit two stop bits ST = 0, Transmit one stop bit bit 5: DIN PE = 1, Parity is enabled for both transmit (state of Pt) and receive. PE = 0, Parity is disabled for both transmit and receive. bit 4: DIN L = 1, 7-bit words (8-bit words if PE = 1) L = 0, 8-bit words (9-bit words if PE = 1) bit 3-0: DIN B3-B0 = XXXX Baud-Rate Divisor select bits. See Table 6. bit 15: DOUT R = 1, Data is available to be read from the receive. register or FIFO. R = 0, Receive register and FIFO are empty. bit 14: DOUT T = 1, Transmit buffer is empty. T = 0, Transmit buffer is full. bit 13-0: DOUT Zeros
______________________________________________________________________________________
19
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
Bits 15 and 14 of the DOUT WRITE CONFIGURATION word (R and T) are sent out of the MAX3140 along with 14 trailing zeros. The use of the R and T bits is optional, but ignore the 14 trailing zeros. Warning! The UART requires stable crystal oscillator operation before configuration (typically ~25ms after power-up). At power-up, compare the WRITE CONFIGURATION bits with the READ CONFIGURATION bits in a software loop until both match. This ensures that the oscillator is stable and the UART is configured correctly.
READ CONFIGURATION Register (D15, D14 = 0, 1) Use the READ CONFIGURATION register to read back the last configuration written to the UART. In this mode, bits 15 and 14 of the DIN configuration word are required to be 0 and 1, respectively, to enable the READ CONFIGURATION mode. Clear bits 13-1 of the DIN word. Bit 0 is the test bit to put the UART in test mode (see the Test Mode section). Table 3 shows the bit assignment for the READ CONFIGURATION register.
MAX3140
Table 3. READ CONFIGURATION Register Bit Assignment (D15, D14 = 0, 1)
BIT DIN DOUT Notes: bit 15: DOUT R = 1, Data is available to be read from the receive register or FIFO. R = 0, Receive register and FIFO are empty. bit 14: DOUT T = 1, Transmit buffer is empty. T = 0, Transmit buffer is full. bit 13: DOUT FEN = 0, FIFO is enabled FEN = 1, FIFO is disabled bit 12: DOUT SHDNo = 1, Software shutdown is enabled. SHDNo = 0, Software shutdown is disabled. bit 11: DOUT TM = 1, Transmit-buffer-empty interrupt is enabled. TM = 0, Transmit-buffer-empty interrupt is disabled. bit 10: DOUT RM = 1, Data available in the receive register or FIFO interrupt is enabled. RM = 0, Data available in the receive register or FIFO interrupt is disabled. bit 9: DOUT PM = 1, Parity-bit-received interrupt is enabled. PM = 0, Parity-bit-received interrupt is disabled. 15 0 R 14 1 T 13 0 FEN 12 0 SHDNo 11 0 TM 10 0 RM 9 0 PM 8 0 RAM 7 0 IR 6 0 ST 5 0 PE 4 0 L 3 0 B3 2 0 B2 1 0 B1 0 TEST B0
bit 8: DOUT RAM = 1, Receiver-activity (shutdown mode)/Framing-error (normal operation) interrupt is enabled. RAM = 0, Receiver-activity (shutdown mode)/Framing-error (normal operation) interrupt is disabled. bit 7: DOUT IR = 1, IrDA mode is enabled. IR = 0, IrDA mode is disabled. bit 6: DOUT ST = 1, Transmit two stop bits. ST = 0, Transmit one stop bit. bit 5: DOUT PE = 1, Parity is enabled for both transmit (state of Pt) and receive. PE = 0, Parity is disabled for both transmit and receive. bit 4: DOUT L = 1, 7-bit words (8-bit words if PE = 1) L = 0, 8-bit words (9-bit words if PE = 1) bit 3-0: DOUT B3-B0 = XXXX Baud-Rate Divisor select bits. See Table 6. bit 15, 14: DIN 0, 1 = Read Configuration bit 13-1: DIN Zeros bit 0: DIN If TEST = 1 and CS = 0, then RTS = 16xBaudCLK TEST = 0, Disables TEST mode.
20
______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
Test Mode The device enters a test mode if bit 0 of the DIN configuration word equals 1 when performing a READ CONFIGURATION. In this mode, if CS = 0, the RTS pin transmits a clock that is 16 times the baud rate. The TX pin is low as long as CS remains low while in test mode. Table 3 shows the bit assignment for the READ CONFIGURATION register. WRITE DATA Register (D15, D14 = 1, 0) Use the WRITE DATA register for transmitting to the TX buffer and receiving from the RX buffer (and RX FIFO when enabled). When using this register, the DIN and DOUT WRITE DATA words are used simultaneously and bits 13-11 for both the DIN and DOUT WRITE DATA words are meaningless zeros. The DIN WRITE DATA word contains the data that is being transmitted, and the DOUT WRITE DATA word contains the data
that is being received from the RX FIFO. Table 4 shows the bit assignment for the WRITE DATA register. To change the RTS pin's output state without transmitting data, set the TE bit high. If performing a WRITE DATA operation, the R bit clears on the falling edge of SCLK's 16th clock pulse if no new data is available.
MAX3140
READ DATA Register (D15, D14 = 0, 0) Use the READ DATA register for receiving data from the RX FIFO. When using this register, bits 15 and 14 of DIN must both be 0. Clear bits 13-0 of the DIN READ DATA word. Table 5 shows the bit assignments for the READ DATA register. Reading all available data clears the R bit and interrupt IRQ. If performing a READ DATA operation, the R bit clears on the falling edge of SCLK's 16th clock pulse if no new data is available.
Table 4. WRITE DATA Register Bit Assignment (D15, D14 = 1, 0)
BIT DIN DOUT Notes: 5, 14: DIN 1, 0 = Write Data bit 13-11: DIN Zeros bit 10: DIN TE = 1, Disables transmit, and only RTS will be updated. TE = 0, Enables transmit. bit 9: DIN RTS = 1, Configures RTS = 0 (Logic Low). RTS = 0, Configures RTS = 1 (Logic High). bit 8: DIN Pt = 1, Transmit parity bit is high. If PE = 1, a high parity bit will be transmitted. If PE = 0, then no parity bit will be transmitted. Pt = 0, Transmit parity bit is low. If PE = 1, a low parity bit will be transmitted. If PE = 0, then no parity bit will be transmitted. bit 7-0: DIN D7t-D0t = Transmitting Data bits. D7t is ignored when L = 1. 15 1 R 14 0 T 13 0 0 12 0 0 11 0 0 10 TE RA/FE 9 RTS CTS 8 Pt Pr 7 D7t D7r 6 D6t D6r 5 D5t D5r 4 D4t D4r 3 D3t D3r 2 D2t D2r 1 D1t D1r 0 D0t D0r
bit 15: DOUT R = 1, Data is available to be read from the receive register or FIFO. R = 0, Receive register and FIFO are empty. bit 14: DOUT T = 1, Transmit buffer is empty. T = 0, Transmit buffer is full. bit 13-11: DOUT Zeros bit 10: DOUT RA/FE = Receive-activity (UART shutdown)/Framing-error (normal operation) bit. bit 9: DOUT CTS = CTS input state. If CTS = 0, then CTS = 1 and vice versa. bit 8: DOUT Pr = Received parity bit. This is only valid if PE = 1. bit 7-0: DOUT D7t-D0t = Received Data bits. D7r = 0 for L = 1.
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21
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Table 5. READ DATA Register Bit Assignment (D15, D14 = 0, 0)
BIT DIN DOUT Notes: bit 15, 14: DIN 0, 0 = Read Data bit 13-0: DIN Zeros bit 15: DOUT R = 1, Data is available to be read from the receive register or FIFO. R = 0, Receive register and FIFO are empty. bit 14: DOUT T = 1, Transmit buffer is empty. T = 0, Transmit buffer is full. 15 0 R 14 0 T 13 0 0 12 0 0 11 0 0 10 0 RA/FE 9 0 CTS 8 0 Pr 7 0 D7r 6 0 D6r 5 0 D5r 4 0 D4r 3 0 D3r 2 0 D2r 1 0 D1r 0 0 D0r
bit 13-11: DOUT Zeros bit 10: DOUT RA/FE = Receive-activity (UART shutdown)/Framing-error (normal operation) bit bit 9: DOUT CTS = CTS input state. If CTS = 0, then CTS = 1 and vice versa. bit 8: DOUT Pr = Received parity bit. This is only valid if PE = 1. bit 7-0: DOUT D7t-D0t = Received Data bits. D7r = 0 for L = 1.
Baud-Rate Generator The baud-rate generator determines the rate at which the transmitter and receiver operate. Bits B3-B0 in the WRITE CONFIGURATION register determine the baudrate divisor (BRD), which divides the X1 oscillator frequency. The on-board oscillator operates with either a 1.8432MHz or a 3.6864MHz crystal, or is driven at X1 with a 45% to 55% duty-cycle square wave. Table 6 shows baud-rate divisors for given input codes, as well as the baud rate for 1.8432MHz and 3.6864MHz crystals. The generator's clock is 16 times the baud rate. Interrupt Sources and Masks Using the READ DATA or WRITE DATA register clears the interrupt IRQ, assuming the conditions that initiated the interrupt no longer exist. Table 7 gives the details for each interrupt source. Figure 15 shows the functional diagram for the interrupt sources and mask blocks. Two examples of setting up an IRQ for the MAX3140 are shown below. Example 1: Setting up only the transmit buffer-empty interrupt. Send the 16-bit word below into DIN of the MAX3140 using the WRITE CONFIGURATION register. This 16-bit word configures the MAX3140 for 9600bps, 8-bit words, no parity, and one stop bit with a 1.8432MHz crystal. binary 1100100000001010 HEX C80A
22
Table 6. Baud-Rate Selection Table*
B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BAUD B2 B1 B0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0** 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DIVISION RATIO 1 2 4 8 16 32 64 128 3 6 12 24 48 96 192 384 BAUD RATE (fOSC = 1.8432MHz) 115.2k** 57.6k 28.8k 14.4k 7200 3600 1800 900 38.4k 19.2k 9600 4800 2400 1200 600 300 BAUD RATE (fOSC = 3.6864MHz) 230.4k** 115.2k 57.6k 28.8k 14.4k 7200 3600 1800 76.8k 38.4k 19.2k 9600 4800 2400 1200 600
*Standard baud rates shown in bold **Default baud rate
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Table 7. Interrupt Sources and Masks--Bit Descriptions
BIT NAME MASK BIT MEANING WHEN SET DESCRIPTION The Pr bit reflects the value in the word currently in the receive-buffer register (oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE = 0), or when parity is enabled and the received bit is 0. An interrupt is issued based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next value read by a READ DATA operation. The R bit is set when new data is available to be read or when data is being read from the receive register/FIFO. FIFO is cleared when all data has been read. An interrupt is asserted as long as R = 1 and RM = 1. This is the RA (RX-transition) bit in shutdown, and the FE (framing-error) bit in operating mode. RA is set if there has been a transition on RX since entering shutdown. RA is cleared when the MAX3140 exits shutdown. IRQ is asserted when RA is set and RAM = 1. FE is determined solely by the currently received data, and is not stored in FIFO. The FE bit is set if a zero is received when the first stop bit is expected. FE is cleared upon receipt of the next properly framed character. IRQ is asserted when FE is set and RAM = 1. The T bit is set when the transmit buffer is ready to accept data. IRQ is asserted low if TM = 1 and the transmit buffer becomes empty. This source is cleared on the rising edge of SCLK`s 16th pulse when using a READ DATA or WRITE DATA operation. Although the interrupt is cleared, poll T to determine transmit-buffer status.
Pr
PM
Received parity bit = 1
R
RM
Data available
RA/FE
RAM
Transition on RX when in shutdown; framing error when not in shutdown
T
TM
Transmit buffer is empty
Q
S R
NEW DATA AVAILABLE DATA READ
RM MASK S TRANSMIT BUFFER EMPTY Q R DATA READ TM MASK IRQ N Q S R PE = 1 AND RECEIVED PARITY BIT = 1 PE = 0 OR RECEIVED PARITY BIT = 0
PM MASK TRANSITION ON RX SHUTDOWN RAM MASK FRAMING ERROR SHUTDOWN RAM MASK
Figure 15. Functional Diagram for Interrupt Sources and Mask Blocks
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
Example 2: Setting up only the data-available (or databeing-read) interrupt. Send the 16-bit word below into DIN of the MAX3140 using the WRITE CONFIGURATION register. This 16-bit word configures the MAX3140 for 9600bps, 8-bit words, no parity, and one stop bit with a 1.8432MHz crystal. binary 1100010000001010 HEX C40A Receive FIFO The MAX3140 contains a receive FIFO for data received by the UART to minimize processor overhead. The receive FIFO is 8 words deep and clears automatically if it overflows. Shutting down the UART also clears the receive FIFO. Upon power-up, the receive FIFO is enabled. To disable the receive FIFO, set the FEN bit high when writing to the WRITE CONFIGURATION register. To check whether the FIFO is enabled or disabled, read back the FEN bit using the READ CONFIGURATION. UART Shutdown In shutdown, the oscillator turns off to reduce power consumption (ICCSHDN UART < 1mA). The UART enters shutdown in one of two ways: by a software command (SHDNi bit = 1) or by a hardware command (SHDN = logic low). The hardware shutdown immediately terminates any transmission in progress. The software shutdown, requested by setting SHDNi bit = 1, is entered upon completing the transmission of the data in both the transmit-shift register and the transmit-buffer register. The SHDNo bit is set when the UART enters shutdown (either hardware or software). The microcontroller (C) can monitor the SHDNo bit to determine when all data has been transmitted, then shut down RS-485 transceivers at that time.
Shutdown clears the receive FIFO, R, RA/FE, D0r-D7r, Pr, and Pt registers and sets the T bit high. Configuration bits (RM, TM, PM, RAM, IR, ST, PE, L, B03, and RTS) can be modified when SHDNo = 1 and CTS can also be read. Even though RA is reset upon entering shutdown, it goes high when a transition is detected on the RX pin. This allows the UART to monitor activity on the receiver when in shutdown. The command to power up (SHDNi = 0) turns on the oscillator when CS goes high if SHDN = logic high, with a start-up time of at least 25ms. This is done by writing to the WRITE CONFIGURATION register, which clears all registers but RTS and CTS. Since the crystal oscillator typically requires at least 25ms to start, the first received characters can be garbled and a framing error may occur.
24
MAX3140
RS-485/RS-422 Transceiver
The RS-485/RS-422 transceiver is equipped with numerous features allowing it to be configured for any RS-485/RS-422 application. Figure 10 shows the MAX3140 functional diagram. Included in the RS485/RS-422 transceiver function is full- and half-duplex selectability, true fail-safe circuitry, programmable slew-rate limiting, receiver input filtering, and phase control circuitry.
Full Duplex or Half Duplex The MAX3140 operates in either full- or half-duplex mode. Drive the H/F pin low, leave it unconnected (internal pull-down), or connect it to GND for full-duplex operation or drive it high for half-duplex operation. In half-duplex mode, the receiver inputs are switched to the driver outputs, connecting outputs Y and Z to inputs A and B, respectively. In half-duplex mode, the internal full-duplex receiver input resistors are still connected to inputs A and B. True Fail-Safe Circuitry The MAX3140 guarantees a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver threshold between -50mV and -200mV. If the differential receiver input voltage (A-B) is greater than or equal to -50mV, RO is logic high. If A-B is less than or equal to -200mV, RO is logic low. In the case of a terminated bus with all transmitters disabled, the receiver's differential input voltage is pulled to 0 by the termination. With the receiver thresholds of the MAX3140, this results in a logic high with a 50mV minimum noise margin. Unlike previous fail-safe devices, the -50mV to -200mV threshold complies with the 200mV EIA/TIA-485 standard. Programmable Slew-Rate Limiting The MAX3140 has several programmable operating modes. Transmitter rise and fall times are programmable at 2500ns, 750ns, or 25ns, resulting in maximum data rates of 115kbps, 500kbps, or 10Mbps, respectively. To select the desired data rate, drive SRL to one of three possible states by using a three-state driver, by connecting it to VCC or GND, or by leaving it unconnected. For 115kbps operation, set the three-state device in high-impedance mode or leave SRL unconnected. For 500kbps operation, drive SRL high or connect it to VCC. For 10Mbps operation, drive SRL low or connect it to GND. SRL can be changed during operation without interrupting data communications.
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
Receiver Input Filtering The receivers of the MAX3140, when operating in 115kbps or 500kbps mode, incorporate input filtering in addition to input hysteresis. This filtering enhances noise immunity with differential signals that have very slow rise and fall times. Receiver propagation delay increases by 20% due to this filtering. Phase Control Circuitry Occasionally, twisted-pair lines are connected backward from normal orientation. The MAX3140 has two pins that invert the phase of the driver and the receiver to correct for this problem. For normal operation, drive TXP and RXP low, connect them to ground, or leave them unconnected (internal pull-down). To invert the driver phase, drive TXP high or connect it to VCC. To invert the receiver phase, drive RXP high or connect it to V CC. Note that the receiver threshold is positive when RXP is high.
1% for reliable operation with other systems. This is accomplished easily with a crystal, and in most cases is achieved with ceramic resonators. Table 8 lists different types of crystals and resonators and their suppliers. The MAX3140's oscillator supports parallel-resonant mode crystals and ceramic resonators, or can be driven from an external clock source. Internally, the oscillator consists of an inverting amplifier with its input (X1) tied to its output (X2) by a bias network that self-biases the inverter at approximately VCC/2. The external feedback circuit, usually a crystal from X2 to X1, provides 180 of phase shift, causing the circuit to oscillate. As shown in the standard application circuit, the crystal or resonator is connected between X1 and X2, with the load capacitance for the crystal being the series combination of C1 and C2. For example, for a 1.8432MHz crystal with a specified load capacitance of 11pF, use 22pF capacitors on either side of the crystal to ground. Series-resonant mode crystals have a slight frequency error, typically oscillating 0.03% higher than specified seriesresonant frequency when operated in parallel mode. Note: It is very important to keep crystal, resonator, and load-capacitor leads and traces as short and direct as possible. Make the X1 and X2 trace lengths and ground tracks short, with no intervening traces. This helps minimize parasitic capacitance and noise pickup in the oscillator, and reduces EMI. Minimize capacitive loading on X2 to minimize supply current. The MAX3140's X1 input can be driven directly by an external CMOS clock source. The trip level is approximately equal to VCC/2. Make no connection to X2 in this mode. If a TTL or non-CMOS clock source is used, ACcouple with a 10nF capacitor to X1. A 2V peak-to-peak swing on the input is required for reliable operation.
MAX3140
Applications Information
Crystals, Oscillators, and Ceramic Resonators
The MAX3140 includes an oscillator circuit derived from an external crystal for baud-rate generation. For standard baud rates, use a 1.8432MHz or 3.6864MHz crystal. The 1.8432MHz crystal results in lower operating current; however, the 3.6864MHz crystal may be more readily available in surface-mount packages. Ceramic resonators are low-cost alternatives to crystals and operate similarly, though the Q and accuracy are lower. Some ceramic resonators are available with integral load capacitors, which can further reduce cost. The trade-off between crystals and ceramic resonators is in initial frequency accuracy and temperature drift. Keep the total error in the baud-rate generator below
Table 8. Component and Supplier List
DESCRIPTION Through-Hole Crystal (HC-49/U) Through-Hole Ceramic Resonator Through-Hole Crystal (HC-49/US) SMT Crystal SMT Ceramic Resonator FREQUENCY (MHz) 1.8432 1.8432 3.6864 3.6864 3.6864 TYPICAL C1, C2 (pF) 25 47 33 39 None (integral) SUPPLIER ECS International, Inc. Murata North America ECS International, Inc. ECS International, Inc. AVX/Kyocera PART NUMBER ECS-18-13-1 CSA1.84MG ECS-36-18-4 ECS-36-20-5P PBRC-3.68B PHONE NUMBER (913) 782-7787 (800) 831-9172 (913) 782-7787 (913) 782-7787 (803) 448-9411
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
9-Bit Networks
The MAX3140 supports a common multidrop communication technique referred to as 9-bit mode. In this mode, the parity bit is set to indicate a message that contains a header with a destination address. Set the MAX3140's parity mask to generate interrupts for this condition. Operating a network in this mode reduces the processing overhead of all nodes by enabling the slave controllers to ignore most message traffic. This relieves the remote processor to handle more useful tasks. In 9-bit mode, the MAX3140 is set up with eight bits plus parity. The parity bit in all normal messages is clear, but is set in an address-type message. The MAX3140's parity-interrupt mask generates an interrupt on high parity when enabled. When the master sends an address message with the parity bit set, all MAX3140 nodes issue an interrupt. All nodes then retrieve the received byte to compare to their assigned address. Once addressed, the node continues to process each received byte. If the node was not addressed, it ignores all message traffic until a new address is sent out by the master. The parity/9th-bit interrupt is controlled only by the data in the receive register and is not affected by data in the FIFO, so the most effective use of the parity/9th-bit interrupt is with FIFO disabled. With the FIFO disabled, received nonaddress words are ignored and not even read from the UART.
SIR IrDA Mode
The MAX3140's IrDA mode communicates with other IrDA SIR-compatible devices, or reduces power consumption in opto-isolated applications. In IrDA mode, a bit period is shortened to 3/16 of a baud period (1.61s at 115,200 baud) (Figure 16). A data zero is transmitted as a pulse of light (TX = logic low, RX = logic high). In receive mode, the RX signal's sampling is done halfway into the transmission of a high level. The sampling is done once, instead of three times, as in normal mode. The MAX3140 ignores pulses shorter than approximately 1/16 of the baud period. The IrDA device that is communicating with the MAX3140 must transmit pulses at 3/16 of the baud period. For compatibility with other IrDA devices, set the format to 8-bit data, one stop, no parity.
256 RS-485 Transceivers on the Bus
The standard RS-485 receiver input impedance is 12k (one unit load), and the standard driver can drive up to 32 unit loads. The MAX3140 has a 1/8-unit-load receiver input impedance (96k), allowing up to 256 transceivers to be connected in parallel on one communication line. Any combination of these devices and/or other RS-485 transceivers with a total of 32 unit loads or less can be connected to the line.
Reduced EMI and Reflections for the RS-485/RS-422 Driver
The MAX3140 with SRL = VCC or unconnected, is slewrate limited, minimizing EMI and reducing reflections caused by improperly terminated cables. Figure 17 shows the driver output waveform and its Fourier analy-
1
0
1
0
0
1
1
0
1
IrDA TX IrDA RX NORMAL RX
20dB/div
0 START
1
0
1
0
0
1
1
0
1 STOP
DATA BITS UART FRAME
0
100kHz/div
1MHz
Figure 16. IrDA Timing
26
Figure 17. Driver Output Waveform and FFT Plot of MAX3140 with SRL = GND, Transmitting at 20kHz
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MAX3140 FIG17
NORMAL UART TX
START
STOP
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
MAX3140 FIG18
A
20dB/div
20dB/div
O
100kHz/div
1MHz
O
100kHz/div
1MHz
Figure 18. Driver Output Waveform and FFT Plot of MAX3140 with SRL = VCC, Transmitting a 20kHz Signal
Figure 19. Driver Output Waveform and FFT Plot of MAX3140 with SRL = Unconnected, Transmitting a 20kHz Signal
sis of a 20kHz signal transmitted with SRL = GND. Highfrequency harmonic components with large amplitudes are evident. Figure 18 shows the same signal for SRL = VCC, transmitting under the same conditions. Figure 18's high-frequency harmonic components are much lower in amplitude, compared with Figure 17's, and the potential for EMI is significantly reduced. Figure 19 shows the same signal for SRL = unconnected, transmitting under the same conditions. In general, a transmitter's rise time relates directly to the length of an unterminated stub, which can be driven with only minor waveform reflections, The following equation expresses this relationship conservatively: Length = tRISE / (10 * 1.5ns/ft) where tRISE is the transmitter's rise time. For example, consider a rise time of 1320ns. This results in excellent waveforms with a stub length up to 90 feet. A system can work well with longer unterminated stubs, even with severe reflections, if the waveform settles out before the UART samples them.
Enable times t ZH and t ZL in the Switching Characteristics tables assume the device was not in a lowpower shutdown state. Enable times tZH(SHDN) and tZL(SHDN) assume the device was shut down. It takes drivers and receivers longer to become enabled from low-power shutdown mode (tZH(SHDN), tZH(SHDN)) than from driver/receiver-disable mode (tZH, tZL).
Driver Output Protection
Two mechanisms prevent excessive output current and power dissipation caused by faults or by bus contention. The first, a foldback current limit on the output stage, provides immediate protection against short circuits over the whole common-mode voltage range (see Typical Operating Characteristics). The second, a thermal shutdown circuit, forces the driver outputs into a high-impedance state if the die temperature becomes excessive.
Line Length vs. Data Rate
The RS-485/RS-422 standard covers line lengths up to 4000 feet. For line lengths greater than 4000 feet, use the repeater application shown in Figure 20. Figures 21, 22, and 23 show the system differential voltage for the parts driving 4000 feet of 26AWG twistedpair wire into 120 loads.
RS-485/RS-422 Transceiver Low-Power Shutdown Mode
Low-power shutdown mode is initiated by bringing both RE high and DE low. RE and DE may be driven simultaneously; the MAX3140 is guaranteed not to enter shutdown if RE is high and DE is low for less than 50ns. If the inputs are in this state for at least 600ns, the device is guaranteed to enter shutdown.
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MAX3140 FIG19
A
27
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Typical Applications
The MAX3140 is designed for bidirectional data communications on multipoint bus transmission lines. The RS-485 transceiver can be used in any RS-485 application due to its numerous features and its programmability. A typical half-duplex circuit for the MAX3140 is shown in Figure 24, and a corresponding half-duplex network is shown in Figure 25. A typical full-duplex circuit for the MAX3140 is shown in Figure 26, and a corresponding full-duplex network is shown in Figure 27. Since the MAX3140's internal UART has IrDA capability, a standard IR transceiver (e.g., the MAX3120) can be used to provide IrDA communication (Figure 28).
MAX3140 (FULL DUPLEX)
A RO RE DE Z DI 120 Y
DI
5V/div
R
120 B
DATA IN
VA - VB
1V/div
D
DATA OUT
RO
5V/div
5s/div
Figure 20. Line Repeater in Full-Duplex Mode
Figure 21. System Differential Voltage at 50kHz Driving 4000 Feet of Cable with SRL = Unconnected
DI
5V/div
DI
5V/div
VA - VB
1V/div
VA - VB
1V/div
RO
5V/div
RO
5V/div
5s/div
2s/div
Figure 22. System Differential Voltage at 100kHz Driving 4000 Feet of Cable with SRL = VCC
Figure 23. System Differential Voltage at 200kHz Driving 4000 Feet of Cable with SRL = GND
28
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
VCC 10k +5V VCC H/F SHDN CTS RTS TX RX UART IRQ DIN DOUT SCLK CS
P
VCC 100k
X1
MAX3140
X2 RO R Z DI DE RE* SRL Y D RXP TXP HALF-DUPLEX RS-485 I/O
*NOTE: TO SHUT DOWN THE RS-485 TRANSCEIVER, DRIVE RE SEPARATELY.
Figure 24. Typical Half-Duplex Operating Circuit
120 DI Z
120 B DE
D
DE RO RE Y B A B A A
D
DI
R R R D
R
RO RE
MAX3140
DI
D
DE
RO RE
DI
DE
RO RE
Figure 25. Typical Half-Duplex RS-485 Network
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29
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
VCC 10k VCC SHDN H/F CTS RTS TX RX RO R UART X1 IRQ DIN DOUT SCLK CS
P
MAX3140
X2 A B Y Z RXP TXP FULL-DUPLEX RS-422 I/O
DI DE RE* SRL
D
*NOTE: TO SHUT DOWN THE RS-485 TRANSCEIVER, DRIVE RE SEPARATELY WITH AN I/O OF A P.
Figure 26. Typical Full-Duplex Operating Circuit
A RO RE DE Z DI
Y 120 120 Z DE B 120 120 B A B A A RE RO
R
B
D
DI
D
Y
R
MAX3140
R
R
RE RO
RE RO
Figure 27. Typical Full-Duplex RS-422 Network
30
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
VCC 10k +5V VCC H/F IRQ DIN DOUT SCLK CS UART IN IrDA MODE TX RX IrDA I/O
MAX3120
P
MAX3140
VCC 100k SOFTWARE NON-IrDA UART RX TX DI DE RTS FLOAT RE* SRL D RO R
X1
X2
Z Y
HALF-DUPLEX RS-485 I/O
RXP TXP
*NOTE: TO SHUT DOWN THE RS-485 TRANSCEIVER, DRIVE RE SEPARATELY.
Figure 28. Typical IR and RS-485 Operating Circuit
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31
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Software Driver
Listing 1 is a C-language outline of an interrupt-driven software driver that interfaces to a MAX3140, providing an intermediate layer between the bit-manipulation subroutine and the familiar PutChar/GetChar subroutines. The user must supply code for managing the transmit and receive queues, as well as the low-level hardware interface itself. The interrupt control hardware must be initialized before this driver is called.
Listing 1. Outline for a MAX3140 Software Driver
32
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Listing 1. Outline for a MAX3140 Software Driver (continued)
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33
SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Listing 1. Outline for a MAX3140 Software Driver (continued)
34
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers
Pin Configuration
TOP VIEW
X2 1 X1 2 CTS 3 RTS 4 RX 5 TX 6 H/F 7 GND 8 RO 9 RE 10 DE 11 DI 12 SRL 13 N.C. 14 28 SHDN 27 IRQ 26 CS 25 SCLK 24 DOUT
___________________Chip Information
TRANSISTOR COUNT: 7479
MAX3140
MAX3140
23 DIN 22 VCC 21 RXP 20 A 19 B 18 Z 17 N.C. 16 Y 15 TXP
QSOP
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SPI/MICROWIRE-Compatible UART with Integrated True Fail-Safe RS-485/RS-422 Transceivers MAX3140
Package Information
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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